C) DIN Connector Assignments

J1/P1 Pin Assignments

Pin Row A Row B Row C Comments
1 D00 BBSY* D08
2 D01 BCLR* D09
3 D02 ACFAIL* D10
4 D03 BG0IN* D11
5 D04 BG0OUT* D12
6 D05 BG1IN* D13
7 D06 BG1OUT* D14
8 D07 BG2IN* D15
9 GND BG2OUT* GND
10 SYSCLK BG3IN* SYSFAIL*
11 GND BG3OUT* BERR*
12 DS1* BR0* SYSRESET*
13 DS0* BR1* LWORD*
14 Write* BR2* AM5
15 GND BR3* A23
16 DTACK* AM0 A22
17 GND AM1 A21
18 AS* AM2 A20
19 GND AM3 A19
20 IACK* GND A18
21 IACKIN* SERLCK* A17
22 IACKOUT* SERDAT* A16
23 AM4 GND A15
24 A07 IRQ7* A14
25 A06 IRQ6* A13
26 A05 IRQ5* A12
27 A04 IRQ4* A11
28 A03 IRQ3* A10
29 A02 IRQ2* A09
30 A01 IRQ1* A08
31 -12V +5V STBY +12V
32 +5V +5V +5V

Notes:

  1. P2 Rows A and C are user defined. They are specified in the VXIbus which is one reason why the VXIbus and VMEbus are not totally compatible.
  2. A01 to A31 is the address bus. Notice it is similar to the MC68000 scheme ie without A0. DS0* and DS1* (DS = Data Strobe) specify the upper or lower portion of the data bus. (rather than having a A0) See the FAQ for comp.sys.m68k for a discussion of this issue.
  3. * means an active low signal.

D) VME64 - a new standard

The regular VMEbus standard accommodates 32 bit address and data buses. Data transfers are 32, 16 and 8 bytes wide. One type of data transfer, called a Block Transfer, allow up to 256 bytes to be transferred with only the start address placed on the address bus once. For the rest of the transfer, the address bus is idle. The VME64 standard utilizes this unused bandwidth to enable 64 bit block transfers. The lower 32 bits are placed on the regular D0 to D31 and the upper 32 bits placed on the idle address bus A01 to A31.

The VME64 standard adds many other advanced features. VME64 is a VITA Standard. This standard, which has recently gained ANSI approval, is backwards compatible with existing VMEbus boards.

For more information: http://www.vita.com/jvita.html