Chapter 12 - Atomic Caesium Clock




Actually La Silla have a mixture of clock system. The older one (1975) is the Atomic Cesium Clock. Today the NTT have a completely different system GPS based. The NTT signal was sended to the 3.6m telescope. In adition, there are new projects to give a GPS signal to all the rest of telescopes all over La Silla. This Atomic Cesium clock have right now problem with is natural obsolescence because its spare parts and the atomic cell itself. In the future the Cesium Clock wiil be consuder as a back up of the GPS system.

The cesium clock system described below is intented to provide the following features:


Universal Tome (UT) in form of display, serial IRIG B code, and BCD parallel.

- Sideral Time (ST) in the same forms

- Square waves at 5 Mhz at 1 Hz signal

- Very haigh precision in those signals requiring very haigh stability frequency sources

- Redundancy in the time generation in order to insure continuous failure free operation over very long periods

- Local power source (in form of a battery) to insure continuous operation in case of main power source failure


To fullfill those requirements the clock system is designed as follow:


- A time base station whose purpose is to generate the primary frequency and the reference Universal Time.

- A time distribution center, able to andle the time in Universal or Sideral form and generate a seial form (so called IRIG B) easy to vehicule on long distances (as far as 4 Km)

- Has meny terminal has needed near the users, which are fed by the IRIG B code and provide for local display and BCD parallel output in either Universal or Sideral Time


Figure 1 shows the block diagram of the Time generation assembly which contains the following parts:


- Cesium beam oscillator as primary frequency standard with its primary clock

- Frequency handling unit

- Three time code generators able to work in either Universal or Sideral time.

- A switching assembly and distribution amplifiers to drive the lines with UT or ST IRIG B code.

- Battery packs to provide for local power sources



This part of the clock system contains the high precision frequency source and the time keeping module.

B1.- Cesium Frequency Standard

The requirement for accuracy implies the use of a cesium beam oscillator as primary frequency source.

Model proposed is referenced XSC manufactured by RHODE & SCHWARZ (specification in the electronic laboratory)

B2.- Time Keeping Module

This is a standard module (ref CADM) manufactured by RHODE & SCHWARZ

This unit which fits mechanically in XSC cabinet allows the following performances:


- Date in Days, hours, minutes and seconds

- 1 Hz pulse output with phase adjustment from 0 to 999999,9 us

- Synchronisation possibility via external pulse.



The time Distribution Center consists of a quartz cristal frequency source (and handler), Time code generators and Distribution Amplifier Unit.

Its purpose is to deliver IRIG B codes to the lines which connect remote users to the time source.

C1.- Frequency Unit (figure 2)

C1.1.- Specifications



- External frequency at 5 Mhz (from cesium)

- 1 Hz pulse with level from 3 V to 30 V to synchronise the 1 Hz output.


- 3 Square waves at 5 Mhz (to drive the TCG)

- 4 pulse outputs at 1 Hz (to drive the TCG)

- Monitoring signals:


- Level alarm on external frequency input

- Level alarm on local oscillator

- Frequency source selected

- Frequency source in operation

- Local oscillator mode (free/locked)

- Locking of local oscillator

- Power source (mains/battery)



- Frequency source (Int/Ext/Automatic)

- Local quartz oscillator mode (free/locked)


C1.2.- Local Frequency Source

The primary clock contains a local frequency source in from of a quartz cristal oscillator.

Model prposed is referenced 1 0 544 B, manufactured by HEWLETT-PACKARD

C1.3.- Frequency handling operation on frequency sources are:


- Shaping and monitoring

Sine Waves at at outputs of source (external or internal) are converted to square by triggers; in addition a watch-dog monitors the presence of those pulses and delivers an alarm signal.

- Switching

The frequency source used may choosen in the following ways:


- manually with the push buttons on front panel

- automatically by the unit; in this case external source is choosen if non alarm condition exist on this source; when an alarm condition occurs the device automatically switches to the local source (in less than 1 us)


C1.4.- Frequency distribution

The switched 5 Mhz logic signal is routed to output logic amplifiers (3 outputs) in order to drive the Time Code Generators of the Time Distribution Center

The 1 Hz input pulse is buffered in 4 amplifiers; three of them are intented to feed Time Code Generators; the last is a spare one.

C1.5.- Local oscillator locking (figure 3)

The purpose of this device is to lock the phase of the local oscillator on that of the external reference.

The schematic shows the different parts


- Frequency divider (1/4) and phase lag

- Product detector and mean value computer; phase adjustment is available by mean of DC component variation.

- Integrator with a time constant of about 1 sec. and damping factor of about 2.

The control voltage is routed to:

- The frequency control input of the quartz oscillator in case the loop is closed

- An analog to digital to analog converter of "tracking" type; the reference voltage (output of integrator) is compared to the analog voltage obtained by a D/A convertion; inequality (+/- some threshold) drives up or down a counter which holds the digital value of the control voltage; in case of alarm one go into two actions:


- supression of motion of the counter (and hence memorisation of last consign value)

- switching of the control input of Xtal from integrator output to A/D/A converter

Resolution of D/A converter is 8 bits; as EFC of Xtal is for full scale variation, thus frequency memorisation is done with better resolution than 5x.


In addition a "Free" position for Xtal control is provided, with an adjustment of fine tuning


C2.- Universal / Sideral Time Code Generator (figure 4)

C2.1.- Specifications



- 5 Mhz frequency (logical level) provided by primary clock

- 1 Hz pulse (logical level)


- IRIG B code with 2,2 Vpp

- Monitoring signals:


-UT/ST mode

IRIG B output valifity

Power source (mains / battery)


C2.2.- ST Frequency Generator

ST second is related to UT second by the equation:



The ratio can also be obtained by dividing 50.000 by (49863 + 375 / 784) with an error of 5.3 X

This is done by implementing a 49863 / 49864 counter and 750 followed by a 34 counter on a 5 Mhz to output a 100 hz sideral frequency.

C2.3.- IRIG B carrier generator

This carrier has a frequency of 1000 Hz; to obtain this value starting from a 100 Hz signal one must perform a frequency multiplication (X10)

This is done by a phase - lock loop which is fed by 100 Hz sideral generated as described; it constains:


- a VCO at 1Khz

- a square to sine converter followedby a trigger

- a divide by ten counter

- the phase comparator and indicator


NB This device is also used in case of UT generation; this procedure simplifies considerably switching between UT and ST generation.

C2.4.- Clock

- UT 100 Hz generator

Is obtained by dividing the incoming frequency at 5 Mhz by 50.000. A group of thumbswitches allows advance of local UT from 0 to 9999 us versus 1Hz reference UT coming from primary clock.

NB This procedure is available only in UT; for ST the synchronisation procedure is as follows:


- set starting ST in hours, minutes, seconds and tens of milliseconds with the thumbswitches and "load" push - button on front panel

- at desired UT time press the "sync" control; the 1Hz external pulse makes ST starting; hence this starting procedure has to be performed once and only once

STo: ST starting time
UTo: UT date for ST starting
Value for STo must computed before starting

- 1 Hz generator and Time Accumulator

100 Hz pulses (either UT or ST) are counted down to 1 Hz; this part of the counting chain may be set to 99 by mean of 1 Hz pulse (only in UT) thus providing a whole phase advance of 999999us.

Time accumulator is built using divide by 60 and 24 counters; the contents of TA are displayed on the front panel on 6 digits, 7 segment . TA control are identical to those of primary clock.



C2.5.- IRIG B Code Generator

It uses 3 sub-assemblies:

- Serializer

Parallel BCD time information (on 20 bits) is serialized by multiplexing technic: rate of multiplexing and bit position in message are extracted from 100 Hz to 1 Hz divider.

- Pulse duration modulation

IRIG B modulation uses 3 durations:


- "0" bit duration: 2 ms
- "1" bit duration: 5 ms
- "R" bit duration: 8 ms


Modulation is performed by multiplexing technic using NRZ output of serializer as data input and 1000 Hz to 1 Hz counter outputs as address inputs.

- Amplitude modulation

IRIG B standard requires for a sine 1000 Hz carrier with an amplitude modulation of 1/3; this is done by varying an Op Amp gain with a field effect transistor used as a switch.

Output is 2,2 Vpp with 50 ohms impedance.

C2.6.- IRIF B Monitoring

It of most importance to check, to some extent, validity of IRIG B output; as the critical point of the chain is in the output amplifier, we implement a monitoring circuit which acts as the input circuit of a remote terminal, i.e., which demodulates the IRIG B code and compare this demodulated signal to the modulating one at input of amplitude modulator; any difference is detected and generates an alarm signal.

C3.- Distribution Amplifier Unit (figure 5)

This unit provides bufferisation and distribution of IRIG B code along the transmittion lines.

C3.1.- Specification


IRIG B code (3inputs).


Two froups of 15 lines each, 2,2 Vpp level with 150 source impedance.


- Two 3 positions rotary switches to route one of the 3 IRIG B input code to the desired output group

- Lamp on front panel to indicate power source in use (mains / battery)

C3.2.- Design

The two groups are housed in the same unit. However, to maintain a high level of reliability each group has its own power supply.

In each group we find 15 amplifiers driven by the common of the source selector switch.

line output is electrically isolated by a transformer.


D1.- Power Supply

Units in the Time Base Station and Distribution Center are powered by two sources.

- AC source in normal operation

- DC source in case of AC source failure.

Autonomies on DC source has been fixed to 8 hours for the Time Base Station (cesium standard + Time keeping module) and hour for the distribution center (Frequency unit + Time Code Generator + Distribution Amplifier Unit).

The general concept retained is that each unit has two power inputs.

- AC line output at 220 V +/- 10% and 50 Hz +/- 2 Hz

- DC line input in range of 22 to 30 V

DC input are fed by battery tailored to the required autonomy.

D1.1.- Unit power supply circuitry (figure 6)

In each unit we find:

- An AC line power transformer followed by a rectifier and filtering cell; this subsystem furnishes a non regulated lightly smoothed DC voltage

- A second small transformer (to measure AC line voltage) and a circuitry to drive a serie pass transistor which switches, on or off the DC input.

- As many DC to DC converters as needed to provide the DC internal voltage of the unit.



Lower switching point for VAC 185 Vrms

Upper switching point for VAC 200 Vrms


D1.2.- DC Sources

Each DC source consists of:

- A battery pack using sealed cadmium - Nickel cells with adequate capacity

- A Charger with two ratings: fast charging during a short time, slow continuous mode

We retained the following equipement

- One pack with 280 WH capacity (minimum needed is 250 WH for 8 hours autonomy) for the cesium beam beam frequency standard and the time keeping module

- One pack with 280 WH capacity (minimum needed is 180 WH for 1 hour autonomy) for the Time Distribution Center.

D2.- Packaging and Technology

As far as possible, components are choosen in CCTU (French Standardization Organization) lists.

- Semiconductors are silicium for discrete types and TTL low power schotky (LS) for integrated types, with few parts in TTL.

- Components are used at worst case charge coefficient 20% below their maximum ratings for voltage and 50% for power.

- Components are hand or machine soldered on double side plated through holes printed circuits boards with a 52 pins gold etched connector.

- Interconnection between card connectors is mode in "miniwrapping" technic.

- I/O connectors are BNC socket and multipin rectangular CANNON D serie.

D3.- Mechanical

D3.1.- Time base Station

Time base station consist of cesium frequency standard (and its Time module) and battery pack

Those two units are tigthted together with a special mechanic assembly and may be installed in either.

- a small 8 units height cabinet (about 400 mm) easy to transport (in order to check clock synchronism against observatories)

- The standard 19" cabinet of the Time distribution center.

D3.2.- Time Distribution Center

All units are housed in 19 inches wide, 2 panel unit height (88 mm) and 500mm depth; they are mounted with streching slides in a cabinet of 36 PU usuable height (manufacturer: TRANSRACK, serie AMBIANCE, color: brown

- this cabinet will receive the Time Base Station assembly during normal operation.


Purpose of those devives is to provide time information at remote places from the Time Center. The media used to vehicle information is the IRIG B serie code. Units may indiferently handle ST or UT IRIG B codes.

E1.- Specification

E1.1.- Input

IRIG B code with level in the range of 0,2 Vpp t 5 Vpp

E1.2.- Output

- BCD time in parallel from seconds to hours on 20 lines; true TTL level fan out of 3,2 mA

- 1Khz pulse TTL compatible (F.o=3,2 mA)

- 1Khz pulse (0,8 duty cycle), some fan-out.

- IRIG B; this is only a duplication of the input connection provided to make easier connection of devices in "daisy" chain.

E1.3.- Power Supply

- AC line 220 V +/-10% at 50 Hz +/-2Hz; no internal battery no provision for DC supplying.

E1.4.- Controls

- Display of time (expressed in hours, minutes and seconds) with 6 flat, 7 segments.

- Display intensity adjustment by front panel potentiometer

- Code level alarm (red light)

E2.- Design (figure 7)

Unit is designed along with three mains sub-assemblies.

E2.1.- Clock

The 1 Khz pulse extracted from code is divided down to 1Hz. This 1 Hz pulse feeds a Time Accumulator (made of divide by 60 and divide by 24 counters)

A parallel access in the TA is installed to allow time setting of this circuit.

Outputs of the TA are:


-BCD parallel to the rear panel connector (via buffers)

- Display on front panel; intensity control is achieved via control of the duty cycle on the "blanking" input of the decoders-drives; this is done by an astable multivibrator whose frequency is about 100 Hz.

- In addition 1 Hz and 1 Khz pulses are output one rear panel via buffers.


E2.2.- IRIG B Decoder

This section includes the following parts:


-Input circuitery: consist of an isolation transformer (with Z>10Kohm at 1Khz) followed by a rectifier and a peak value detector; outputs of this section are:


- 1Khz carrier quasi square

- pulses for the large amplitude waves of the incoming signal.


- Demodulator: using the preceding signal, it outputs a RZ signal which is equal to the modulating one with a fix delay of 1ms.

- Decoder: extracts the 1Hz sychronising pulse (detection of two consecutive marquers) and an NRZ signal.

NOTE: Decoding is not affected if the input modulation is +/-1 ms in error

- Deserializer: The NRZ information is shifted in a 10 bits serial to parallel register which, a the end of IROG B word (1/10 of message), holds the information to be loaded in TA


E2.3.- Synchronizing Circuitry

Those circuits are used to perform the coupling between decoder and clock sections

-At frequency level

Jitter on 1Khz extracted from IRIG B code (at output of demodulator may range between 50 and 250 us depending on code level, phase distortion on lines and circuitry balancing. To fullfill the specification of 20 us maximum jitter one need to provide for a phase noise "cleaner"; this is the reason for the Phase Lock Loop we put between the output of demodulator and input of dividing chain.

Performances for this PLL are:


-Capture range = 1000 +/- 100Hz

- Lock Range = 1000 +/- 200Hz

-Wn = 10 rad/sec

- Damping factor = 2

- Residual jitter = from 5 to 20 us


- At Data Level

Decoded 1 Hz pulse is use to synchronize the 1Khz to 1 Hz dividing chain

Parallel data available at output of serial to parallel register is loaded into time accumulator by pulses extracted from that chain.

E3.- Technology and Mechanical

The same general rules for technology as for Time Center may be applied to terminals.

E3.1.- Packing

The whole electronic circuits lays on two printed circuit boards

- one board for the clock, decoder and power supply

- one double (sandwich) board for the display.

E3.2.- Power Supply

Unit supplied by AC mains (220 V +/-10% at 50 Hz +/-2Hz). A power transformer followed by rectifier and filtering capacitors gives the non regulated DC voltages.

- High voltage (180 V) for display tubes is not regulates

- Low voltage (5 V) for logic circuits is regulated.

E3.3.- Mechanical

Unit fits in a 19 inches wide standard with 2 panels unit heigh (88 mm) and 250 mm depth..

Input/output connectors are located on rear panel.


F1.- Initial Time setting

This is done by transporting the Time Base Station to the Bureau International de l'Heure and synchronising the Time keeping module by a 1 Hz reference pulse.

F2.- Normal Operation

In normal operation the Time Base Station outputs the 5 Mhz and 1 Hz signals to the frequency Unit which is in "Locked" mode (provided the AUTO mode and XSC operational) outputs the 5 Mhz issued from cesium to and 1 Hz to the Time code generation.

Time setting


- Choose the USTG mode (UT of ST)

- Program starting Time (in hours, minutes, seconds and 1/100 sec for ST and Usec for UT)

- Load the program

- Start operation when desired (is automatically synchronised by the incoming 1 Hz pulse


- at some computed UT in ST mode

- at desired UTo in UT mode


- Repeat process described for the three USTG.


IRIG B Selection

Select on DAU the type of IRIG B code (ST or UT) which is going to send one each group of 15 lines.

F3.- Maintenance Operation

This is the case when removing the Time Base Station to check for stability

-Choose the INTERNAL source in Frequency unit: this switches the PLL off and puts the memory sub-assembly in Memory mode; one can remove now the external frequency source (cesium).

- Their is no difference in operation for the Time Distribution Center.

F4.- Remote Units

One has only feed the unit with an IROG B code (either ST or UT) with proper level (from 0,2 Vpp to 5 Vpp) and switch power on.


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